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HI5634
ODUCT OBSOLETE PR T D REPLACEMEN DE Data Sheet NO RECOMMEN nter at nical Support Ce contact our Tech www.intersil.com/tsc or 1-888-INTERSIL
P RE L I M I N A RY
July 2000
File Number
4745.1
High Performance Programmable Phase-Locked Loop for LCD Applications
The HI5634 is a low cost but very high-performance frequency generator for line-locked and genlocked high resolution video applications. Utilizing an advanced low voltage CMOS mixed signal technology, the HI5634 is an effective clock solution for video projectors and displays at resolutions from VGA to beyond UXGA The HI5634 offers pixel clock outputs in both differential (to 250MHz) and single-ended (to 150MHz) formats. Digital phase adjustment circuitry allows user control of the pixel clock phase relative to the recovered sync signal. A second differential output at half the pixel clock rate enables deMUXing of multiplexed A/D converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. The advanced PLL utilizes either its internal programmable feedback divider or an external divider. The device is programmed by a standard I2C-bus1/4(R) serial interface.
Features
* Pixel Clock Frequencies up to 250MHz * Very Low Jitter * Digital Phase Adjustment (DPA) for Clock Outputs * Balanced PECL Differential Outputs * Single-Ended SSTL_3 Clock Outputs * Double-Buffered PLL/DPA Control Registers * Independent Software Reset for PLL/DPA * External or Internal Loop Filter Selection * Uses 3.3V Supply. Inputs are 5V Tolerant. * I2C-bus Serial Interface can Run at Either Low Speed (100kHz) or High Speed (400kHz) * Lock Detection
Applications
* LCD Monitors and Video Projectors * Genlocking Multiple Video Subsystems * Frequency Synthesis
Simplified Block Diagram
LOOP FILTER
Pinout
CLK
OSC HSYNC I2C INTERFACE PHASE LOCKED LOOP DIGITAL PHASE ADJUST
HI5634 (SOIC) TOP VIEW
VDDD VSSD SDA SCL 1 2 3 4 5 6 7 8 9 24 IREF 23 CLK/2+ (PECL) 22 CLK/2- (PECL) 21 CLK+ (PECL) 20 CLK- (PECL) 19 VSSQ 18 VDDQ 17 CLK (SSTL) 16 CLK/2 (SSTL) 15 FUNC (SSTL) 14 LOCK/REF (SSTL) 13 I2CADR
CLK/2 FUNC
Ordering Information
PART NUMBER HI5634CB TEMP. RANGE ( oC) 0 to 70 PACKAGE 24 Ld SOIC PKG. NO. M24.3
PDEN EXTFB HSYNC EXTFIL EXTFILRET
VDDA 10 VSSA 11 OSC 12
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
HI5634 Pin Descriptions
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 PIN NAME VDDD VSSD SDA SCL PDEN EXTFB HSYNC EXTFIL EXTFILRET VDDA VSSA OSC I2CADR TYPE PWR PWR IN/OUT IN IN IN IN IN IN PWR PWR IN IN DESCRIPTION Digital Supply Digital Ground Serial Data Serial Clock PFD Enable External Feedback In Horizontal Sync External Filter External Filter Return Analog Supply Analog Ground Oscillator I2C Address I2C-Bus (Note 1) I2C-Bus (Note 1) Suspends Charge Pump (Note1) External Divider Input to PFD (Note1) Clock Input to PLL (Note1) External PLL Loop Filter External PLL Loop Filter Return 3.3V for Analog Circuitry Ground for Analog Circuitry Input From Crystal Oscillator Package (Notes 1, 2) Chip I2C Address Select Low = 4Dh Read, 4Ch Write High = 4Fh Read, 4Eh Write Displays PLL or DPA Lock or REF Input SSTL_3 Selectable HSYNC Output SSTL_3 Driver to ADC DeMUX Input SSTL_3 Driver to ADC 3.3V to Output Drivers Ground for Output Drivers Inverted PECL Driver to ADC. Open Drain Output. PECL Driver to ADC. Open Drain Output. Inverted PECL Driver to ADC DeMUX Input. Open Drain Output. PECL Driver to ADC DeMUX Input. Open Drain Output. Reference Current for PECL Outputs COMMENTS 3.3V to Digital Sections
14 15 16 17 18 19 20 21 22 23 24 NOTES:
LOCK/REF (SSTL) FUNC (SSTL) CLK/2 (SSTL) CLK (SSTL) VDDQ VSSQ CLK- (PECL) CLK+ (PECL) CLK/2- (PECL) CLK/2+ (PECL) IREF
OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT IN
Lock Indicator/Reference Function Output Pixel Clock/2 Out Pixel Clock Out Output Driver Supply Output Driver Ground Pixel Clock Out Pixel Clock Out Pixel Clock/2 Out Pixel Clock/2 Out Reference Current
1. These LVTTL inputs are 5V tolerant. 2. Connect to ground if unused.
4-2
OSC_DIV REG 7[0-6] LOCK/REF (14)
PDEN (5)
Block Diagram
OSC (12) PD_POL REG 0[1] LOCK LOGIC EN_PLS REG 0[6] EXTFIL (8) XFILRET (9) 1 MUX PHASE/ FREQ IN_SEL REG 7[7] FBK_POL REG 0[3] INT FILTER DPA_LOCK REG 12[0] PFD PLL_LOCK REG 1[0-2] REG 12[1] FIL_SEL REG 4[7] POST SCALER DIVIDER DETECTOR PUMP SELECT CHARGE VCO FILTER 0 PECL BIAS PDEN REG 0[0] EN_DLS REG 0[7]
OSC
DIVIDER
4-3
PSD REG 1[4-5] OUTPUT FEEDBACK DIVIDER SCALER FBD1 FBD0 REG 3[0-3] REG 2[0-7] DPA_OS REG 4[0-5] DPA_RES REG 5[0-1] DIGITAL PHASE ADJUST CK2_INV REG 6[5] 1 MUX 0 FUNC_SEL REG 0[5]
REF_POL REG 0[2]
HSYNC (7)
IREF (24)
FBK_SEL REG 0[4]
EXTFB (6)
1
OUT_SCL REG 6[6-7]
MUX
0
HI5634
CLK (17) OE_TCK REG 6[1] + CLK+ (21)
SDA (3)
I 2C
CLK- (20) OE_PCK REG 6[0] CLK/2 (16) OE_T2 REG 6[3] + CLK/2+ (23) CLK/2- (22) OE_P2 REG 6[2] FUNC (15) OE_F REG 6[4]
SCL (4)
INTERFACE
I2CADR (13)
POWER
ON
RESET
HI5634
Absolute Maximum Ratings
VDDA, VDDD, VDDQ (Measured to VSS). . . . . . . . . . . . . . . . . 4.3V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . VSSD -0.3V to +5.5V Analog Outputs . . . . . . . . . . . . . . . . . . VSSA -0.3V to VDDA +0.3V Digital Pouts. . . . . . . . . . . . . . . . . . . . . VSSQ -0.3V to VDDQ +0.3V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . >2kV
Thermal Information
Thermal Resistance (Typical, Note 3)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 260oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Voltage Range (VDDA, VDDD, VDDQ to VSS) . . . . . . 3.0V to 3.6V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER DC SUPPLY CURRENT Supply Current, Digital Supply Current, Output Drivers Supply Current, Analog
Per Operating Conditions Listed Above, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IDDD IDDQ IDDA
VDDD = 3.6V VDDQ = 3.6V, No Output Drivers Enabled VDDA = 3.6V
-
-
25 6 5
mA mA mA
DIGITAL INPUTS (SDA, SCL, PDEN, EXTFB, HSYNC, OSC, I2CADR) Input High Voltage Input Low Voltage Input Hysteresis Input High Current Input Low Current Input Capacitance IIH IIL CIN VOL IOUT = 3mA. VOH = 6.0V Maximum, as Determined by the External Pull-up Resistor. VIH = VDD VIL = 0 VIH VIL 2 VSS-0.3 0.2 5.5 0.8 0.6 10 200 10 V V V A A pF
SDA (IN OUTPUT MODE: SDA IS BIDIRECTIONAL) Output Low Voltage 0.4 V
PECL OUTPUTS (CLK+, CLK-, CLK/2+, CLK/2-) Output High Voltage Output Low Voltage (Note 4) VOH VOL RO fHSYNC fOSC tr tP tS tF t0 t1 IOUT = 0 IOUT = Programmed Value 1 < VO < 2V Reg 7[7] = 0 Reg 7[7] = 1 1.0 VDD V V
SSTL_3 OUTPUTS (CLK, CLK/2, FUNC, LOCK/REF) Output Resistance AC INPUT CHARACTERISTICS HSYNC Input Frequency OSC Input Frequency TIMING CHARACTERISTICS (Note 5) REF Output Transition Times PECL CLK Output Transition Times SSTL CLK Output Transition Times FUNC Output Transition Times HSYNC to REF Delay REF to PECL Clock Delay Rise Time/Fall Time Rise Time/Fall Time Rise Time/Fall Time Rise Time/Fall Time 11.3 -1.0 2.8/1.8 1.0/1.2 1.6/0.7 1.2/1.0 11.5 0.8 12 2.2 ns ns ns ns ns ns 0.008 0.02 10 100 MHz MHz 80
4-4
HI5634
Electrical Specifications
PARAMETER PECL Clock Duty Cycle PECL Clock to SSTL Clock Delay PECL Clock to FUNC Delay PECL Clock to PECL Clock/2 Delay PECL Clock to SSTL Clock/2 Delay SSTL Clock Duty Cycle NOTES: 5. Measured at 3.6V 0oC, 135MHz output frequency, PECL Clock lines to 75 termination, SSTL Clock lines unterminated, 20pF load. Transition times vary based on termination. See the "Output Timing Diagram" for details. 4. VOL must not fall below the minimum specified level or the IOUT value may not be maintained. Per Operating Conditions Listed Above, Unless Otherwise Specified (Continued) SYMBOL t2, t3 t4 t5 t6 t7 t8, t9 TEST CONDITIONS MIN 45 0.2 1.5 1.0 1.1 45 TYP 50 0.75 1.9 1.3 1.4 50 MAX 55 1.2 2.3 1.5 1.8 55 UNITS % ns ns ns ns %
Application Information
Overview
The HI5634 addresses stringent graphics system line locked and genlocked applications and provides the clock signals required by high-performance video A/D converters. Included are a phase locked loop (PLL) with a 500MHz voltage controlled oscillator (VCO), a digital phase adjustment to provide a user programmed pixel clock delay, the means for deMUXing multiplexed A/D Converters, and both balanced programmable (PECL) and single-ended (SSTL_3) high-speed clock outputs.
Digital Phase Adjustment
The digital phase adjustment allows addition of a programmable delay to the pixel clock output, relative to the recovered HSYNC signal. The ability to add delays is particularly useful when multiple video sources must be synchronized. A delay of up to one pixel clock period is selectable in the following increments: 1/64 period for pixel clock rates to 40MHz 1/32 period for pixel clock rates to 80MHz 1/16 period for pixel clock rates to 160MHz
Output Drivers and Logic Inputs
The HI5634 utilizes low voltage TTL (LVTTL) inputs as well as SSTL_3 (EIA/JESD8-8) and low voltage PECL (pseudoECL) outputs, operating at 3.3V supply voltage. The LVTTL inputs are 5V tolerant. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated unterminated.
Phase-Locked Loop
The phase-locked loop is optimized for line-locked applications, for which the inputs are horizontal sync signals. A high-performance Schmitt trigger preconditions the HSYNC input, whose pulses can be degraded if they are from a remote source. This preconditioned HSYNC signal is provided as a clean reference signal with a short transition time (in contrast, the signal that a typical PC graphics card provides has a transition time of tens of nanoseconds). A second high frequency input such as a crystal oscillator and a 7-bit programmable divider can be selected. This selection allows the loop to operate from a local source and is also useful for evaluating intrinsic jitter. A 12-bit programmable feedback divider completes the loop. Designers can substitute an external divider. Either the conditioned HSYNC input or the loop output (recovered HSYNC) is available at the FUNC pin, aligned to the edge of the pixel clock.
I 2C-bus Serial Interface
The HI5634 utilizes the industry standard I2C-bus serial interface. The interface uses 12 registers: one write-only, eight read/write, and three read-only. Two HI5634 devices can be addressed, according to the state of the I2 CADR pin. When the pin is low, the read address is 4Dh, and the write address is 4Ch. When the pin is high, the read address is 4Fh, and the write address is 4Eh. The I2C-bus serial interface can run at either low speed (100kHz) or high speed (400kHz) and provides 5V tolerant input.
PC Board Layout
Use a PC board with at least four layers: one power, one ground, and two signal. No special cutouts are required for power and ground planes. All supply voltages must be supplied from a common source and must ramp up together. Flux and other board surface debris can degrade the performance of the external loop filter. Ensure that the HI5634 area of the board is free of contaminants.
Automatic Power-On-Reset Detection
The HI5634 has automatic power-on-reset detection circuitry and it resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required.
4-5
HI5634
Specific Layout Guidelines
1. Digital Supply (VDDD) - Bypass pin 1 (VDDD) to pin 2 (VSSD) with 4.7F and 0.1F capacitors, located as close as possible to the pins. Traces must be maximally wide and include multiple surface-etched vias to the appropriate plane. 2. External Loop Filter - The use of an external loop filter is strongly recommended in all designs. Locate loop filter components as close to pins 8 and 9 (EXTFIL and EXTFILRET) as possible. Typical loop filter values are 6.8k for the series resistor, 3300pF RF-type capacitor for the series capacitor, and 150pF for the shunt capacitor. 3. Analog PLL Supply (VDDA) - Decouple pin 10 (VDDA) with a series ferrite bead. Bypass the supply end of the bead with 4.7F and 0.1F capacitors. Bypass pin 10 to pin 11 (VSSA) with a 0.1F capacitor. Locate these components as close as possible to the pins. Traces must be maximally wide and have multiple surface-etched vias to the power or ground planes. 4. PECL Current Set Resistor - Locate PECL current set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to ground with a 0.1F capacitor. 5. PECL Outputs - Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 characteristic impedance, presuming 0.067 in. between layers. Locate the optional series "snubbing" resistors as close as possible to the pins. If the termination resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground planes (these termination resistors are omitted if the load device implements them internally). 6. Output Driver Supply (VDDQ) - Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with 4.7F and 0.1F capacitors, located as close as possible to the pins. Traces must be maximally wide and include multiple surface-etched vias to the appropriate plane. 7. SSTL_3 Outputs - SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmission line system at higher-output frequencies. With terminated outputs, the considerations of item 5, "PECL Outputs" apply. See JEDEC documents JESD8-A and JESD8-8.
VDD
VMIN VTH = 1.8V tD
SSTL_3 Outputs
Unterminated Outputs
In the HI5634, unterminated SSTL output pins display exponential transitions similar to those of rectangular pulses presented to RC loads. The 10-90% rise time is typically 1.6ns, and the corresponding fall time is typically 700ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor determining high frequency performance of these single-ended outputs. Typically, no termination is required for the LOCK/REF, FUNC, and CLK/2 outputs nor for CLK outputs up to approximately 135MHz.
Terminated Outputs
SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance. Use of transmission line techniques enables use of longer traces between source and driver without increasing ringing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet LVTTL VIH and VIL requirements, the intrinsic rise and fall times of HI5634 SSTL outputs are only slightly improved by termination in a low impedance. The HI5634 SSTL output source impedance is typically less than 60. Termination impedance of 100 reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs.
VDD 330
Power Supply Considerations
The HI5634 incorporates special internal power-on-reset circuitry that requires no external reset signal connection. The supply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the HI5634, the supply voltage at the part must be reduced below the threshold voltage (VTH) of the power-onreset circuit. The supply voltage must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset state is latched. The amount of time (tD) to hold the voltage in a reset state varies with the design. However, a typical value of 10ms should be sufficient.
HI5634
SSTL_3 OUTPUT
150
SINGLE LVTTL LOAD
4-6
HI5634
I 2C Register Map Summary
REGISTER NUMBER 0h NAME Input Control ACCESS R/W BIT NAME PDEN PD_POL REF_POL FBK_POL FBK_SEL FUNC_SEL EN_PLS EN_DLS 1h Loop Control R/W PFD0-2 Reserved PSD0-1 Reserved 2h 3h FDBK Div 0 FDBK Div 1 R/W R/W FDB0-7 FDB8-11 Reserved 4h DPA Offset R/W DPA_OS0-5 Reserved FIL_SEL 5h DPA Control R / W DPA_RES0-1 METAL_REV 6h Output Enables R/W OE_PCK OE_TCK OE_P2 OE_T2 OE_F CK2_INV OUT_SCL 7h OSC_DIV R/W OSC_DIV 0-6 IN_SEL 8h Reset Write DPA PLL 10h 11h 12h Chip Ver Chip Rev RD_REG Read Read Read CHIP VER CHIP REV DPA_LOCK PLL_LOCK Reserved RESET BIT # VALUE 0 1 2 3 4 5 6 7 0-2 3 4-5 6-7 0-7 0-3 4-7 0-5 6 7 0-1 2-7 0 1 2 3 4 5 6-7 0-6 7 0-3 4-7 0-7 0-7 0 1 2-7 1 0 0 0 0 0 1 0 0 0 0 0 FF F 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 x x 17 01 N/A N/A 0 DESCRIPTION Phase Detector Enable (0 = External Enable, 1 = Always Enabled) Phase Detector Enable Polarity (0 = Not Inverted, 1 = Inverted) External Reference Polarity (0 = Positive Edge, 1 = Negative Edge) External Feedback Polarity (0 = Positive Edge, 1 = Negative Edge) External Feedback Select (0 = Internal Feedback, 1 = External) Function Out Select (0 = Recovered HSYNC, 1 = Input HSYNC) Enable PLL Lock/Ref Status Output (0 = Disable, 1 = Enable) Enable DPA Lock/Ref Status Output (0 = Disable, 1 = Enable) Phase Detector Gain Reserved Post Scaler Divider (0 = /2, 1 = /4, 2 = /8, 3 = /16) Reserved PLL Feedback Divider LSBs (Bits 0-7) PLL Feedback Divider MSBs (Bits 8-11) Reserved Digital Phase Adjustment Offset Reserved Loop Filter Select (0 = External, 1 = Internal) DPA Resolution (0 = 16 Delay Elements, 1 = 32, 2 = Reserved, 3 = 64) Metal Mask Revision Number Output Enable for PECL PCLK Outputs (0 = High Z, 1 = Enabled) Output Enable for STTL_3 CLK Output (0 = High Z, 1 = Enabled) Output Enable for PECL CLK/2 Outputs (0 = High Z, 1 = Enabled) Output Enable for STTL_3 CLK/2 Output (0 = High Z, 1 = Enabled) Output Enable for STTL_3 FUNC Output (0 = High Z, 1 = Enabled) CLK/2 Invert (0 = Not Inverted, 1 = Inverted) SSTL Clock Scaler (0 = /1, 1 = /2, 2 = /4, 3 = /8) Osc Divider Modulus Input Select (0 = HSYNC Input, 1 = Osc Divider) Writing xAh Resets DPA and Loads Working Register 5 Writing 5xh Resets PLL and Loads Working Registers 1-3 Chip Version 23 Decimal (17 Hex) Initial Value 01h. Value Increments With Each All Layer Change. DPA Lock Status (0 = Unlocked, 1 = Locked) PLL Lock Status (0 = Unlocked, 1 = Locked) Reserved
Identifies Double Buffered Registers. Working Registers are Loaded During Software PLL Reset. Identifies Double Buffered Registers. Working Registers are Loaded During Software DPA Reset.
4-7
HI5634 Software Programming Flow
INITIALIZE REGISTERS 0, 6, 7
CHANGE PLL AND/OR DPA SETTINGS
SET DPA OUTPUT DELAY TO 0
REG4[0-5] = 0
NO
CHANGE PLL FREQ. ?
YES
SET INPUT, PFD GAIN, POST SCALER, AND FEEDBACK DIVIDER
REGS 0, 1, 2, 3
PLL SOFTWARE RESET
REG8 = 50h (NOTE 6)
WAIT ~ 1ms
NO
PLL LOCKED ? YES REG12[1] = 1?
REG5
SET DPA RESOLUTION
DPA SOFTWARE RESET
REG8 = 0Ah (NOTE 7)
WAIT ~ 1ms
SELECT DESIRED DPA OUTPUT DELAY
REG4[0-5]
DONE
NOTES: 6. Updates working Registers 1-3. 7. Updates working Resister 5.
4-8
HI5634 Detailed Register Description
Register: 0h
BIT NAME PDEN PD_POL REF_POL FBK_POL FBK_SEL FUNC_SEL BIT # 0 1 2 3 4 5
Name: Input Control
RESET VALUE 1 0 0 0 0 0
Access: Read/Write
DESCRIPTION
Phase/Frequency Detector Enable - 0 = External Enable (Phase/Frequency Detector controlled by PDEN (pin 5) only), 1 = Always Enabled (default). Phase/Frequency Detector Enable Polarity - Used only when (Reg0 [0]=0). 0 = Not inverted (default, PDEN input (pin 5) is active high),1 = Inverted (PDEN input (pin 5) is active low). Phase/Frequency Detector External Reference Polarity - Edge of input signal on which Phase Detector triggers. 0 = Rising Edge (default), 1 = Falling Edge. External Feedback Polarity - Edge of EXTFB (pin 6) signal on which Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1). 0 = Positive Edge (default), 1 = Negative Edge. External Feedback Select - 0 = Internal Feedback (default), 1 = External Feedback. Function Output Select - Selects re-clocked output to FUNC (pin 15). 0 = Recovered HSYNC (default, regenerated HSYNC output), 1 = External HSYNC (Schmitt-trigger conditioned input from HSYNC (pin 7)). Outputs PLL Lock Status (Reg12[1]) on LOCK/REF pin. Outputs DPA Lock Status (Reg12[0]) on LOCK/REF pin. Bits 6, 7 enable multiple functions at LOCK/REF output (pin 14), as shown in table at right. EN_PLS 0 0 1 1 1 EN_DLS 0 1 0 1 1 IN_SEL N/A N/A N/A 0 1 LOCK/REF (14) 0 1 if DPA Locked, 0 Otherwise 1 if PLL Locked, 0 Otherwise Post Schmitt Trigger HSYNC(7) XOR REF_POL FOSC / OSC_DIV
EN_PLS
6
1
EN_DLS
7
0
Register: 1h
BIT NAME PFD0-2 BIT # 0-2
Name: Loop Control Register
RESET VALUE 0 Phase/Frequency Detector Gain.
Access: Read/Write (Note 8)
DESCRIPTION BIT 2 0 0 0 0 1 1 1 1 BIT 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 1 0 1 0 1 PFD GAIN (A/2 RAD) 1 2 4 8 16 32 64 128
Reserved PSD0-1
3 4-5
0 0
Reserved Post-Scaler Divider - Divides the output of the VCO prior to the DPA and Feedback Divider. BIT 5 0 0 1 1 BIT 4 0 1 0 1 PSD DIVIDER 2 (Default) 4 8 16
Reserved
6-7
0
Reserved
4-9
HI5634
Register: 2h, 3h
REG # 2h 3h 3h BIT NAME FBD0-7 FBD8-11 Reserved
Name: Feedback Divider Registers
BIT # 0-7 0-3 4-7 RESET VALUE FF F
Access: Read/Write (Note 8, 9)
DESCRIPTION
PLL Feedback Divider LSBs (0-7). When Bit 0 = 0, the total number of pixels is even. When Bit 0 = 1, the total number of pixels is odd. PLL Feedback Divider MSBs (8-11). Reserved REG 3 3 2 1 0 7 6 5 REG 2 4 3 2 1 0
Feedback Divider Modulus =
12 Feedback Divider Modulus 4103
+8 Access: Read/Write
DESCRIPTION
Register: 4h
BIT NAME DPA_OS0-5 BIT # 0-5
Name: DPA Offset Register
RESET VALUE 0
Digital Phase Adjustment Offset - Selects clock edge offset in discrete steps from zero to one clock period minus one step. Resolution (number of delay elements per clock cycle) is selected by DPA_RES0-1 (Reg 5[0-1]). Note: Offsets equal to or greater than one clock period are neither recommended nor supported. Example: For DPA_RES0-1=01h, the clock can be delayed from 0 to 31 steps. Reserved Selects external loop filter (0) or internal loop filter (1). The use of an external loop filter is strongly recommended for all designs.
Reserved FIL_SEL
6 7
0 0
Register: 5h
BIT NAME DPA_RES0-1 BIT # 0-1
Name: DPA Control Register
RESET VALUE 3 Digital Phase Adjustment (DPA) Resolution Select. Use of the DPA above 160MHz is not recommended.
Access: Read/Write (Note 10)
DESCRIPTION BIT 1 0 0 1 1 BIT 0 0 1 0 1 BIT 7 1 0 1 0 1 1 1 1 BIT 6 1 1 0 0 1 1 1 1 DELAY ELEMENTS 16 32 Reserved 64 BIT 5 1 1 1 1 0 1 1 1 12 BIT 4 1 1 1 1 1 0 1 1 40 BIT 3 1 1 1 1 1 1 0 1 BIT 2 1 1 1 1 1 1 1 0 24 CLK RANGE (MHz) 48 80 160
METAL_REV
2-7
0
Metal Mask Revision Number - After power-up, register bits 2-7 must be written with 111111. After this write, a read indicates the metal mask revision, as shown in the table at right.
REVISION A B C1 C2 D E F G
NOTES: 8. Double buffered registers. Actual working registers are loaded during software PLL reset. See Register 8h for details. 9. The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the HI5634 generates between HSYNCs. Program these registers with the total number of horizontal pixels per line minus 8. 10. Double buffered register. Actual working registers are loaded during software DPA reset. See Register 8h for details.
4-10
HI5634
Register: 6h
BIT NAME OE_PCK OE_TCK OE_P2 OE_T2 OE_F CK2_INV OUT_SCL BIT # 0 1 2 3 4 5 6-7
Name: Output Enable Register
RESET VALUE 0 0 0 0 0 0 0
Access: Read/Write
DESCRIPTION
Output Enable for CLK Outputs (PECL) - 0 = High Z (default), 1 = Enabled. Output Enable for CLK Output (SSTL_3) - 0 = High Z (default), 1 = Enabled. Output Enable for CLK/2 Outputs (PECL) - 0 = High Z (default), 1 = Enabled. Output Enable for CLK/2 Output (SSTL_3) - 0 = High Z (default), 1 = Enabled. Output Enable for FUNC Output (SSTL_3) - 0 = High Z (default), 1 = Enabled. CLK/2 Invert - 0 = Not Inverted (default), 1 = Inverted. Clock (CLK) Scaler. BIT 7 0 0 1 1 BIT 6 0 1 0 1 CLK DIVIDER 1 2 4 8
Register: 7h
BIT NAME OSC_DIV0- 6 IN_SEL BIT # 0-6 7
Name: Oscillator Divider Register
RESET VALUE 0 1
Access: Read/Write
DESCRIPTION
Oscillator Divider Modulus - Divides the input from OSC (pin 12) by the set modulus. The modulus equals the programmed value, plus 2. Therefore, the modulus range is from 3 to 129. Input Select - Selects the input to the Phase/Frequency Detector 0 = HSYNC, 1 = Osc Divider (default).
Register: 8h
BIT NAME DPA Reset BIT # 0-3
Name: Reset Register
RESET VALUE X
Access: Write Only
DESCRIPTION VALUE XA 5X 5A RESETS DPA PLL DPA and PLL
Writing XAh to this register resets DPA working Register 5. Writing 5Xh to this register resets PLL working Registers 1-3.
PLL Reset
4-7
X
Register: 10h
BIT NAME CHIP VER BIT # 0-7
Name: Chip Version Register
RESET VALUE 17 Chip Version 23 (17h).
Access: Read Only
DESCRIPTION
Register: 11h
BIT NAME CHIP REV BIT # 0-7
Name: Chip Revision Register
RESET VALUE 01+
Access: Read Only
DESCRIPTION
Initial value 01h. +Value increments with each all-layer change.
Register: 12h
BIT NAME DPA_LOCK PLL_LOCK Reserved BIT # 0 1 2-7
Name: Status Register
RESET VALUE N/A N/A 0
Access: Read Only
DESCRIPTION
DPA Lock Status (Refer to Register 0h, bits 6 and 7). 0 = Unlocked, 1 = Locked. PLL Lock Status (Refer to Register 0h, bits 6 and 7). 0 = Unlocked, 1 = Locked. Reserved
4-11
HI5634 I 2C Data Format (Notes 11-14)
RANDOM REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 XWA 7 Bit Address Register Address
A
Data
AP
RANDOM REGISTER READ PROCEDURE S 0 1 0 0 1 1 XWA 7 Bit Address Register Address
A S 0 1 0 0 1 1 X RA
7 Bit Address Data
AP
SEQUENTIAL REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 XWA 7 Bit Address Register Address
A
Data
A
Data
A
AP
SEQUENTIAL REGISTER READ PROCEDURE S 0 1 0 0 1 1 XWA 7 Bit Address Direction: NOTES: 11. All values are transmitted with the most significant bit first and the least significant bit last. 12. The value of the X-bit equals the logic state of pin 13 (I2CADR). 13. R = Read Command = 1, W = Write Command = 0. 14. S = Start Condition, A = Acknowledge, A = No Acknowledge, P = Stop Condition. See "I2C Data Characteristics" for description. Register Address
A S 0 1 0 0 1 1 X RA
7 Bit Address Data
A Data
AP
= Bus Host to Device
= Device to Bus Host
I 2C Data Characteristics
SDA
SCL DATA LINE STABLE: DATA VALID CHANGE OF DATA ALLOWED
BIT TRANSFER ON THE I2C BUS SDA
SCL
S START CONDITION
P STOP CONDITION
START AND STOP CONDITIONS
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION 1 2 7 8 9 CLOCK PULSE FOR ACKNOWLEDGMENT
ACKNOWLEDGE ON THE I2C BUS
NOTE: These waveforms are from "The I2C bus and how to use it," published by Philips Semiconductor. The document can be obtained from: http://www-us2.semiconductors.philips.com/acrobat/various/i2c_bus_specification_1995.pdf.
4-12
AC Timing Characteristics Overview
HSYNC
REF
4-13
PECL CLK-
PECL CLK+
SSTL CLK
FUNC
HI5634
EVEN TOTAL PIXELS
PECL CLK/2+
PECL CLK/2-
SSTL CLK/2
ODD TOTAL PIXELS
PECL CLK-
PECL CLK+
SSTL CLK/2
Timing when Register 2[0] = 0 (Total Number of Pixels is Even). Timing when Register 2[0] = 1 (Total Number of Pixels is Odd).
HI5634 Output Timing Diagram
HSYNC REF PECL CLKPECL CLK+ SSTL CLK tS t4 t8 t9 t0
tR
t1
t2
t3
tP
tF FUNC t5 EVEN TOTAL PIXELS PECL CLK/2+ PECL CLK/2SSTL CLK/2 t7 t6
Timing when Register 2[0] = 0 (Total Number of Pixels is Even).
4-14
HI5634 Typical Performance Curves
700 FREQUENCY (SLOW: 3.0V AT 70oC) FREQUENCY (NOMINAL: 3.3V AT 30 oC) 600 FREQUENCY (FAST: 3.6V AT 0 oC) JITTER (3.0V AT 70oC) 500 JITTER (3.3V AT 30oC) JITTER (3.6V AT 0oC) 400 300 200 100 0 100 0 JITTER (ps) 20 18 16 DELAY RANGE (ns) 14 12 10 8 6 4 2 0 0 4 8 12 DPA OFFSET SETTING (# OF STEPS) 16 DPA_RES 0-1 = 00h 50MHz - SVGA AT 72Hz 157.5MHz - SXGA AT 85Hz
VCO FREQUENCY (MHz)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 VCO VOLTAGE (V)
FIGURE 1. VCO FREQUENCY AND JITTER vs VCO VOLTAGE
FIGURE 2. DPA DELAY vs OFFSET SETTING (16 ELEMENTS)
45 40 35 DELAY RANGE (ns) 30 25 20 15 10 5 0 0
DPA_RES 0-1 = 01h 25.175MHz - VGA AT 60Hz 78.75MHz - XGA AT 75Hz DELAY RANGE (ns)
90 80 70 60 50 40 30 20 10
DPA_RES 0-1 = 03h 12.27MHz - NTSC 39.8MHz - SVGA AT 60Hz
4
8 12 16 20 24 DPA OFFSET SETTING (# OF STEPS)
28
32
0
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64 DPA OFFSET SETTING (# OF STEPS)
FIGURE 3. DPA DELAY vs OFFSET SETTING (32 ELEMENTS)
FIGURE 4. DPA DELAY vs OFFSET SETTING (64 ELEMENTS)
4-15
HI5634 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 10.00 0.25 0.40 24 0o MAX 2.65 0.30 0.51 0.32 15.60 7.60 10.65 0.75 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914 0.394 0.010 0.016 24 0o
MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992 0.419 0.029 0.050 8o
A1 B C D E e H
C
e
B 0.25(0.010) M C AM BS

A1 0.10(0.004)
0.05 BSC
1.27 BSC
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
4-16

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